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? semiconductor components industries, llc, 2012 october, 2012 ? rev. 0 1 publication order number: ncp4355/d ncp4355 secondary side smps off mode controller for low standby power description the ncp4355 is a secondary side smps controller designed for use in applications which require extremely low no load power consumption. the device is capable of detecting ?no load? conditions and entering the power supply into a low consumption off mode. during off m ode, the primary side controller is turned off and energy is provided by the output capacitors thus eliminating the power consumption required to maintain regulation. during off mode, the output voltage relaxes and is allowed to decrease to an adjustable level. once more energy is required, the ncp4355 automatically restarts the primary side controller by onoff current that flows through onoff optocoupler. the ncp4355 controls the primary controller with an ?active on? signal, meaning that it only drives optocoupler current during on mode to minimize consumption during off mode. during normal power supply operation, the ncp4355 provides integrated voltage feedback regulation, replacing the need for a shunt regulator. the a and c versions include a current regulation loop in addition to voltage regulation. the ncp4355 includes a led driver pin (except c version) implemented with an open drain mosfet driven by a 1 khz square wave with a 12.5% duty cycle for indication purpose. the ncp4355 is available in soic ? 8 package. device options ncp4355a ncp4355b ncp4355c adjustable vmin no yes yes current regulation yes no yes led driver yes yes no features ? operating input voltage range: 3.5 v to 36.0 v ? supply current < 100 a ? 0.5% reference voltage accuracy (t j = 25 c) ? constant voltage and constant current (a and c versions) control loop ? indication led pwm modulated driver (except ncp4355c) ? these are pb ? free and halide free devices typical applications ? offline adapters for notebooks, game stations and printers ? high power ac ? dc converters for tvs, set ? top boxes, monitors etc. http://onsemi.com soic ? 8 d suffix case 751 1 8 xxxxx = specific device code a = assembly location l = wafer lot y = year w = work week = pb ? free package xxxxx alywx 1 8 see general marking information in the device marking section on page 16 of this data sheet. device marking information
ncp4355 http://onsemi.com 2 sw1 management power reset voltage regulation off mode detection 1 khz, 12% d.c. oscillator sw3 current regulation ota power reset ota vcc isns sw2 led vsns gnd offdet fbc sink only sink only enabling vcc powerreset s r q q on/off figure 1. simplified block diagram ? ncp4355a i driveon v dd v ref v cc 10%v cc v ref i biasv 0.9 x v ref v refc i biasv v dd sw1 management power reset voltage regulation off mode detection 1 khz, 12% d.c. oscillator sw3 power reset ota vcc sw2 led vsns gnd offdet min output voltage fbc sink only vmin enabling vcc powerreset s r q q on/off figure 2. simplified block diagram ? ncp4355b i driveon v dd v ref v cc v refm 10%v cc i biasv 0.9 x v ref v ref v dd i biasv
ncp4355 http://onsemi.com 3 sw1 management power reset voltage regulation off mode detection sw3 current regulation ota power reset ota vcc isns vsns gnd offdet fbc sink only sink only vcc powerreset s r q q on/off min output voltage vmin figure 3. simplified block diagram ? ncp4355c v cc v dd v ref i driveon v dd v refc i biasv v ref 0.9 x v ref 10%v cc v refm i biasv enabling
ncp4355 http://onsemi.com 4 pin function description ncp4355a ncp4355b ncp4355c pin name description 8 8 8 vcc supply voltage pin 7 7 7 gnd ground 1 1 1 vsns output voltage sensing pin, connected to output voltage divider 2 2 2 offdet off mode detection input. voltage divider provides adjustable off mode detection threshold ? 3 3 vmin minimum output voltage adjustment 3 ? 4 isns current sensing input for output current regulation, connect it to shunt resistor in ground branch. 4 4 ? led pwm led driver output. connected to led cathode with current define by external serial resistance 6 6 6 fbc output of current sinking ota amplifier or amplifiers driving feedback op- tocoupler?s led. connect here compensation network (networks) as well. 5 5 5 on/off on mode current sink. this output keeps primary control pin at low level in on mode. absolute maximum ratings rating symbol value unit input voltage v cc ? 0.3 to 40.0 v on/off, fbc, led voltage v onoff , v fbc , v led ? 0.3 to v cc + 0.3 v vsns, isns, offdet, vmin voltage v sns , v isns , v offdet , v min ? 0.3 to 10.0 v led current i led 10 ma junction temperature t j ? 40 to 150 c storage temperature t stg ? 60 to 150 c esd capability, human body model (note 1) esd hbm 2000 v esd capability, machine model (note 1) esd mm 250 v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. this device series incorporates esd protection and is tested by the following methods: esd human body model tested per jesd22 ? a114f esd machine model tested per jesd22 ? a115c latchup current maximum rating tested per jedec standard: jesd78d.
ncp4355 http://onsemi.com 5 electrical characteristics 0 c t j 125 c; v cc = 15 v; unless otherwise noted. typical values are at t j = +25 c. parameter test conditions symbol min typ max unit maximum operating input voltage v cc 36.0 v vcc uvlo v cc rising v ccuvlo 3.75 4.00 4.25 v v cc falling 3.22 3.50 3.78 vcc uvlo hysteresis v ccuvlohys 0.4 0.5 v quiescent current in regulation ncp4355a i cc 125 155 a ncp4355b 107 135 ncp4355c 115 155 quiescent current in off mode v sns < 1.12 v i ccoff 90 110 a voltage control loop ota transconductance sink current only gm v 1 s reference voltage 3.8 v v cc 36.0 v, t j = 25 c v ref 1.244 1.250 1.256 v 3.8 v v cc 36.0 v, t j = 0 ? 85 c 1.240 1.250 1.264 3.8 v v cc 36.0 v, t j = 0 ? 125 c 1.230 1.250 1.270 sink current capability in regulation, v fbc > 1.5 v i sinkv 2.5 ma in off mode, v fbc > 1.5 v 1.2 1.5 2.0 ma inverting input bias current in regulation i biasv ? 100 100 na in off mode, v sns > 1.12 v ? 2.6 ? 2.3 ? 1.9 a inverting input bias current threshold in off mode v snsbiasth 1.07 1.12 1.17 v current control loop ota (except ncp4355b) transconductance sink current only gm c 3 s reference voltage v refc 60.0 62.5 65.0 mv sink current capability v fbc > 1.5 v i sinkc 2.5 ma inverting input bias current i sns = v refc i biasc ? 100 100 na minimum voltage comparator (except ncp4355a) threshold voltage v refm 355 377 400 mv hysteresis output change from logic high to logic low v minh 40 mv off mode detection comparator threshold value 2.5 v v cc 36.0 v v offdetth 10% v cc v v cc = 15 v 1.47 1.50 1.53 v hysteresis output change from logic high to logic low v offdeth 40 mv led driver (except ncp4355c) switching frequency f swled 1 khz duty cycle d led 10.0 12.5 15.0 % switch resistance i led = 5 ma r sw2 50 on mode control sink current in on mode, v onoff > 0.6 v i driveon 140 160 180 a
ncp4355 http://onsemi.com 6 typical characteristics figure 4. v ref at v cc = 15 v figure 5. v ref at t j = 25 c t j ( c) v cc (v) 100 80 60 40 20 0 ? 20 ? 40 1.22 1.23 1.24 1.25 1.26 1.27 1.28 1.29 36 30 24 18 12 6 0 1.22 1.23 1.24 1.25 1.26 1.27 1.28 1.29 figure 6. v refc at v cc = 15 v figure 7. v refc at t j = 25 c t j ( c) v cc (v) 100 80 60 40 20 0 ? 20 ? 40 62.0 62.1 62.3 62.4 62.5 62.7 62.9 63.0 36 30 24 18 12 6 0 figure 8. v refm at v cc = 15 v figure 9. v refm at t j = 25 c t j ( c) v cc (v) 350 360 370 380 390 400 410 350 360 370 380 390 400 410 v ref (v) v ref (v) v refc (mv) v refc (mv) v refm (mv) v refm (mv) 120 62.2 62.6 62.8 120 62.0 62.1 62.3 62.4 62.5 62.7 62.9 63.0 62.2 62.6 62.8 100 80 60 40 20 0 ? 20 ? 40 120 36 30 24 18 12 6 0
ncp4355 http://onsemi.com 7 typical characteristics figure 10. v ccuvlo figure 11. v offdetth at v cc = 15 v t j ( c) t j ( c) 100 80 60 40 20 0 ? 20 ? 40 3.4 3.5 3.6 3.7 3.9 4.0 4.1 4.2 1.47 1.48 1.49 1.50 1.51 1.52 1.53 figure 12. i onoff at v cc = 15 v figure 13. i biasv at v cc = 15 v, v sns > v snsbiasth t j ( c) t j ( c) 135 140 145 150 160 165 170 175 ? 2.6 ? 2.5 ? 2.4 ? 2.3 ? 2.2 ? 2.1 ? 2.0 ? 1.9 figure 14. i cc in regulation at v cc = 15 v for ncp4355b figure 15. i cc in regulation at t j = 25 c for ncp4355b t j ( c) v cc (v) 70 75 80 90 100 105 115 120 36 30 24 18 12 6 0 v cc (v) v offdetth (v) i onoff ( a) i biasv ( a) i cc ( a) i cc ( a) 3.8 120 vccuvlo_r vccuvlo_f 100 80 60 40 20 0 ? 20 ? 40 120 100 80 60 40 20 0 ? 20 ? 40 120 155 100 80 60 40 20 0 ? 20 ? 40 120 100 80 60 40 20 0 ? 20 ? 40 120 85 95 110 70 75 80 90 100 105 115 120 85 95 110
ncp4355 http://onsemi.com 8 typical characteristics figure 16. i cc in off mode at v cc = 15 v, v sns < v snsbiasth , for ncp4355b figure 17. i cc in off mode at t j = 25 c, v sns < v snsbiasth , for ncp4355b t j ( c) v cc (v) 36 30 24 18 12 6 0 figure 18. voltage ota current sink capability in regulation figure 19. voltage ota current sink capability in off mode t j ( c) t j ( c) 2.5 2.6 2.8 2.9 3.1 3.2 3.4 3.5 1.2 1.3 1.4 1.5 1.7 1.8 1.9 2.0 figure 20. current ota current sink capability figure 21. led switching frequency at v cc = 15 v t j ( c) t j ( c) 2.5 2.6 2.8 2.9 3.1 3.2 3.3 3.5 0.8 0.9 1.0 1.1 1.2 1.3 1.4 i cc_offmode ( a) i cc_offmode ( a) i sinkv (ma) i sinkv (ma) i sinkc (ma) f swled (khz) 70 75 80 90 100 105 100 80 60 40 20 0 ? 20 ? 40 120 85 95 110 60 65 70 75 80 90 100 105 85 95 110 60 65 100 80 60 40 20 0 ? 20 ? 40 120 2.7 3.0 3.3 100 80 60 40 20 0 ? 20 ? 40 120 1.6 100 80 60 40 20 0 ? 20 ? 40 120 2.7 3.0 3.4 100 80 60 40 20 0 ? 20 ? 40 120
ncp4355 http://onsemi.com 9 typical characteristics figure 22. r sw2 at v cc = 15 v t j ( c) 30 40 50 60 70 80 90 100 r sw2 ( ) 100 80 60 40 20 0 ? 20 ? 40 120
ncp4355 http://onsemi.com 10 application information typical application circuits for ncp4355x are shown in figure 24, figure 25 and figure 26. each ic version contains different features. please see device options table or block diagrams for detail information. ncp4355a does not have a vmin pin for setting the minimum voltage level, therefore it needs a special circuit shown in figure 24 in the dashed box. this is needed for correct detection of load connection in off mode. the same circuit can be used for other versions when high speed detection of load connection is needed. supply voltage the ic is supplied through vcc pin. supply voltage should be taken from output voltage in range from 4.5 v up to 36 v. power supply voltage should be separated from output voltage by a diode d3 and some energy should be stored in a vcc cap c6. cap should be high enough to keep enough energy for onoff optocoupler and ncp4355x before primary controller is started. time constant of the vcc cap c6 and the ic supply current should be smaller than time constant of power supply output filter and maximum output current in off mode. vcc pin should also be decoupled by 100 nf decoupling cap c5. voltage regulation path the output voltage is detected on the vsns pin by the r4, r5 and r6 voltage divider. this voltage is compared with the internal precise voltage reference. the voltage difference is amplified by gm v of the transconductance amplifier. the amplifier output current is connected to the fbc pin. the compensation network is also connected to this pin to provide frequency compensation for the voltage regulation path. this fbc pin drives an optocoupler that provides regulation of primary side. the optocoupler is supplied via direct connection to vout line through resistor r1. regulation information is transferred through the optocoupler to the primary side controller where its fb pin is usually pulled down to reduce energy transferred to secondary output. the vsns voltage divider is shared with vmin voltage divider. the shared voltage divider can be connected in two ways as shown in figure 23. the divider type is selected based on the ratio between v min and v out . when the condition of equation 1 is true, divider type 1 should be used. v min v out v refm v ref (eq. 1) output voltage for divider type 1 can be computed by equation 2 v out v ref r4 r5 r6 r5 r6 (eq. 2) and for type 2 by equation 3. v out v ref r4 r5 r6 r6 (eq. 3) figure 23. shared dividers type current regulation path (a and c versions only) the output current is sensed by the shunt resistor r11 in series with the load. voltage drop on r11 is compared with internal precise voltage reference v refc at i sns transcon ? ductance amplifier input. voltage difference is amplified by gm c to output current of amplifier, connected to fbc pin. compensation network is connected between this pin and isns input to provide frequency compensation for current regulation path. resistor r12 separates compensation network from sense resistor. compensati on network works into low impedance without this resistor that significantly decreases compensation network impact. current regulation point is set to current given by equation 4. i outlim v refc r11 (eq. 4) off mode detection off mode operation is advantageous for ultra low or zero output current condition. the very long off time and the ultra low power mode of the whole regulation system greatly reduces the overall consumption. the output voltage is varying between nominal and minimal in off mode. when output voltage decreases below set (except ncp4355a) minimum level, primary controller is switch on until output capacitor c1 is charged again to the nominal voltage. the off mode detection is based on comparison of output voltage and voltage loaded with fixed resistances (d2, c2, r7 and r8). figure 27 shows detection waveforms. when output voltage is loaded with very low current, primary controller goes into skip mode (primary controller stops switching for some time). while output capacitor c1 is discharged very slowly (no load condition), a fixed load r7 and r8 discharges the capacitor c2 faster than load current discharges output voltage on c1. once offdet pin voltage is lower than v offdetth (this threshold is derived from v cc that is very close to v out ),
ncp4355 http://onsemi.com 11 off mode is detected. in off mode sw1 is switched off and no i onoff current is going through on/off pin. the primary controller?s rem pin voltage increases and primary ic goes in to off mode. i biasv current flow from vsns pin to feedback divider is also activated when off mode is detected. this current increases voltage at vsns pin and due to it voltage ota sinks reduced current through regulation optocoupler. ota stops to sink current when vsns voltage drops below v ref . i biasv current disappears when vsns voltage is lower than 90% of v ref . this feature helps to avoid primary side switching when off mode is detected at secondary side and primary side is waiting for correct information at rem pin. minimum output voltage detection (except ncp4355a) minimum output voltage level defines primary controller restart from off mode. it can be set by shared voltage divider with voltage regulation loop. when vmin voltage drops below v refm , off mode is ended and primary controller restarts. ncp4355a has no external adjustment and uses the internal minimum voltage level specified by minimum falling operation supply voltage and special load detection circuit for faster detection of load connection (t2, r16 and r17 at figure 24). principe of load connection detection is that when load is connected, output capacitor c1 is discharged faster than c6 capacitor by ic supply current. voltage across d3 increases and when there is enough voltage to open t2 some current is injected into offdet divider. v oltage at offdet pin goes above 10% of v cc and off mode ends. this circuit can also be used with b and c versions to dramatically speed up wakeup time from off mode. if this circuit is not used, it is necessary to wait for c6 discharge below vcc uvlo falling level before the primary controller is restarted. led driver (except ncp4355c) led driver is active when vcc is higher than v ccmin and output voltage is in regulation (it is off during off mode). led driver consists of an internal power switch controlled by pwm modulated logic signal and an external current limiting resistor r3. led current can be computed by equation 5 i led v out v f_led r3 (eq. 5) pwm modulation is used to increase efficiency of led. operation in off mode description operation waveforms in off mode and transition into off mode with primary controller are shown in figure 28. figure shows waveforms from the first start (1) of the convertor. at first, primary controller charges vcc capacitor over the v ccon level (2). when primary v cc is over this level (3), primary controller starts to operate and v out is slowly rising according to primary controller start up ramp to nominal voltage (4). when v out is high enough, vcc capacitor is charged from auxiliary winding. primary fb pin voltage is above regulation range until v out is at set level. once v out is at set level, the secondary controller starts to sink current from optocoupler led?s and primary fb voltage is stabilized in regulation region. with nominal output power (without skip mode) offdet pin voltage is higher than v offdetth (typically 10% of v cc ). after some time, the load current decreases to low level (5) and primary convertor uses skip mode (6) to keep regulation of output voltage at set level and save some energy. the skip mode consists of few switching cycles followed by missing ones to provide limited energy by light load. the number of missing cycles allows regulation for any output power. while both c1 and c2 are discharged during the missing cycles, c2 discharge will be faster than c1 without output current, v offdet drops below v offdetth and off mode is detected (7). this situation is shown in figure 27 in detail. when off mode is detected, current into onoff pin stops to flow (7) and voltage at primary rem pin increases over threshold level that forces primary controller into off mode. internal pull ? up current i biasv is switched on (7), vsns pin voltage increases (thanks to i biasv ) and voltage amplifier sinks reduced current at time (8), when vsns is higher than v ref (9), to keep primary fb voltage below switching level until rem pin voltage is high enough. i biasv current stops when vsns voltage drops below 90% of v ref . discharging of c1 continues (10) until output voltage drops below level set by voltage divider at vmin pin (except ncp4355a where minimum v out is defined only by vcc uvlo) (11). onoff current starts to flow, primary rem voltage decreases and primary vcc voltage is rising (12). primary controller starts to operate, when vcc voltage is enough and fb voltage is at regulation area (13). output capacitor c1 is recharged (14) to set voltage. if there is still light load condition primary controller goes to skip mode (15) again and after some time secondary controller detects off mode by very light or no load condition (16) and whole cycle is repeated. fast restart from off mode the ic ends off mode when a load is connected to the output and v out is discharged to v min level. there exists another connection that allows transition to normal mode faster without waiting some time for v out to discharge to v min (it is necessary to use it with ncp4355a). this schematic is shown at figure 24 in dashed box. the basic idea is that c6 is discharged by the ic faster than c1 by output load in off mode. when an output load is applied, capacitor c1 is discharged faster and this creates the voltage drop at d3. when there is enough voltage at d3, t2 is conducting and current is injected into the offdet divider through r16. offdet voltage higher than 10% of v cc ends off mode and on/off current starts to flow . primary controller leaves off mode because voltage at rem pin increase above off mode detection threshold.
ncp4355 http://onsemi.com 12 normal operation waveforms for typical load detection connection and improved load detection waveforms are shown in figure 29. figure 30 shows waveforms for ncp4355a (without vmin detection) in off mode and when load is c onnected during off mode. it can be seen that the application is waiting not for low v out , but for low v cc and then off mode is ended. d1 c1 c2 vout d2 r4 r1 r5 r7 c3 r9 r8 r11 c4 r10 r3 led vsns gnd offdet fbc ~vin vcc fb gnd drv cs hv vcc vcc led1 opto1 c5 r13 c7 c8 c10 d4 t1 r14 d5 d6 ncp4355a r12 vcc d8 d7 d3 r2 on/off c9 rem opto2 opto1 opto2 isns c6 t2 r15 r16 optional for other versions figure 24. typical application schematic for ncp4355a figure 25. typical application schematic for ncp4355b d1 c1 c2 vout d2 r4 r1 r5 r6 r7 c3 r9 r8 r3 led vsns gnd offdet fbc vmin ~vin vcc fb gnd drv cs hv vcc vcc led1 opto1 c5 r13 c7 c8 c10 d4 t1 r14 d5 d6 ncp4355b vcc d8 d7 d3 r2 on/off c9 rem opto2 opto1 opto2 c6
ncp4355 http://onsemi.com 13 d1 c1 c2 vout d2 r4 r1 r5 r6 r7 c3 r9 r8 r11 c4 r10 vsns gnd offdet fbc vmin fb gnd drv cs hv vcc vcc opto1 c5 r13 c7 c8 c10 d4 t1 r14 d5 d6 ncp4355c r12 vcc d8 d7 d3 r2 on/off c9 rem opto2 opto1 opto2 isns c6 figure 26. typical application schematic for ncp4355c vcc ~vin primary controller activity very low or no load detected, off mode activated normal operation skip off mode figure 27. off mode detection i out v offdet 10% v out (v cc )
ncp4355 http://onsemi.com 14 on on skip skip off off 2 4 start ? up and regulation 6 light load ? > skip mode 8 very light load ? > off mode 10a 10b 10c 12 14 15 16 very light load ? > off mode status vmin threshold 1 khz 12% wide pulses 1 khz 12% wide pulses 1 3 5 7 9 11 13 compressed time figure 28. typical application states and waveforms in off mode with active on primary controller start up, i out nominal or low very low i out activates off mode with rarely c out charging v ref v cc_prim v ccon v aux v fb_prim i fbc i led v out i out i onoff v sns v min v offdet 10% v cc v rem_prim i biasv switched on i biasv switched off max i fbc at off mode fbc sink current disappears ? > lower current consumption application powered from c out very light load ? > skip mode c out charging v out < v min ? > i onoff starts flow, primary v cc is rising v out is close to minimum set voltage long time of c out discharging primary v cc cap is charged by dss fbc sink current disappears ? > lower current consumption application powered from c out
ncp4355 http://onsemi.com 15 vmin level primary side start delay no load load is connected vout is discharged faster primary off mode ends typical load detection behavior v offdet v remprim v out v cc i out secondary side detects low v out no load load is connected vmin level t2 is conducting primary side start delay primary off mode ends voltage delivered through t2 and r16 improved load detection behavior figure 29. typical and improved load detection comparison waveforms v offdet v remprim v out v cc i out
ncp4355 http://onsemi.com 16 vccmin level primary side start delay no load load is connected vout is discharged faster primary off mode ends detection primary side figure 30. typical load detection of ncp4355a without external detection circuit waveforms v offdet v remprim v out v cc i out delay start delay secondary side detects low v ccmin ordering information device marking adjustable v min current regulation led driver package shipping ncp4355adr2g ncp4355a no yes yes soic ? 8 (pb ? free) 2500/tape & reel ncp4355bdr2g ncp4355b yes no yes soic ? 8 (pb ? free) 2500/tape & reel ncp4355cdr2g ncp4355c yes yes no soic ? 8 (pb ? free) 2500/tape & reel
ncp4355 http://onsemi.com 17 package dimensions soic ? 8 nb case 751 ? 07 issue ak seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751 ? 01 thru 751 ? 06 are obsolete. new standard is 751 ? 07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ? x ? ? y ? g m y m 0.25 (0.010) ? z ? y m 0.25 (0.010) z s x s m 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intelle ctual property. a listing of scillc?s pr oduct/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising ou t of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary ove r time. all operating parameters , including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associ ated with such unintended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 ncp4355/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loca l sales representative

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